Branch prediction and resolution apparatus for a superscalar computer processor
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United States of America Patent
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Feb 25, 1997
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app pub date -
Feb 9, 1995
filing date -
Jul 31, 1992
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Abstract
An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
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