Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film
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United States of America Patent
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Mar 4, 1997
Grant Date -
N/A
app pub date -
Feb 2, 1994
filing date -
Dec 16, 1993
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Abstract
A method for fabricating an MOS transistor having a source/drain region of shallow junction and a thin silicide film is disclosed. The present method takes advantage of the phase separation of the Ti-excessed titanium nitride film and is capable of forming a thin silicide film in a once metal thermal annealing process. The method employs dopant implant to the titanium nitride and silicide and thermal anneal for diffusion to form source and drain regions.
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