Closed loop clock recovery for synchronous residual time stamp
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United States of America Patent
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Mar 4, 1997
Grant Date -
N/A
app pub date -
Mar 31, 1995
filing date -
Mar 31, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.
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