Importance

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Abstract

A novel apparatus, for use with a microcomputer, for detecting an erroneous input clock signal and/or an input supply voltage to the microcomputer and providing a reliable reset signal thereto, comprises a converter for converting a differential signal representing the phase difference between the input clock signal and a feedback clock signal into a differential voltage and for generating a reference clock signal having a number of logic high and logic low states in response to the differential voltage, wherein the feedback clock signal represents a previously generated reference clock signal; a first comparator for comparing the differential voltage and the input supply voltage with first and second predetermined threshold values, respectively, to detect first and second error signals and for generating an error decision signal based on the first and the second error signals; a circuit, responsive to the error decision signal and a counting value state signal denoting a previously provided reset signal, for selectively producing a zero value, a first or a second non-zero counted value; and a second comparator for comparing the zero value, the first or the second non-zero counted value with a third predetermined threshold value, to thereby provide the reliable reset signal to the microcomputer for the initialization thereof, and to the circuit as the counting value state signal.

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First Claim