Importance

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Abstract

A clock generation circuit (23) is provided for use with a data display device and a calculation unit, with the calculation unit performing a calculation in a calculation mode resulting in data which is displayed on the data display device. The clock generation circuit generates a first clock signal (CK2) and a second clock signal (CK1). The second clock signal (CK1) is generated by a circuit (52) only during a calculation mode. A clock switching circuit (54) selects, in dependence upon whether the calculation mode is being executed, between a clock signal (CKD) derived from the signal (CK1) and an independently-produced clock signal (CKI) for use as the first clock signal (CK2). Thus, power is conserved by turning off the circuit (52) during a pure display mode and by turning off an oscillator (24) which generates the signal (CKI) during a calculation mode.

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First Claim