Computer-aided design methods and apparatus for multilevel interconnect technologies
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United States of America Patent
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Mar 11, 1997
Issued Date -
N/A
app pub date -
Sep 25, 1995
filing date -
Jun 2, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel on-chip and off-chip interconnects. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI, PCB, and MCM interconnects. Four subsystems are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design mode with performance browsing, goal-directed synthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet-style graphical user interface.
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