Importance

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Abstract

A Write/Load cache protocol is described which may be used for maintaining cache coherency and performing barrier synchronization in multiprocessor computer systems, and for cooperating with prefetch mechanisms to allow data to be loaded into a central processor unit's (CPU) cache (in both single and multiprocessor systems) in anticipation of future memory references. The new protocol is defined such that when a cache observes a Write/Load command (and associated data item) on a bus to which the cache is attached, the cache is accessed and (a) if the data item is in the cache, the new value of the data item from the bus is copied into and replaces the data item in cache; and (b) if the data item is not in the cache, a new data item is created therein (preferably using the normal cache replacement policy), and the value of the data item on the bus is loaded into the cache. Thus, a protocol is provided which allows cache to be loaded via an external entity, i.e., other than the processor being directly serviced by the cache.

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First Claim