Chip stack and method of making same
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United States of America Patent
Stats
-
Mar 18, 1997
Grant Date -
N/A
app pub date -
Apr 13, 1995
filing date -
Apr 13, 1995
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An integrated circuit chip stack includes a stack of chip packages mounted on a substrate. Each chip package includes a plastic packaged chip mounted within a central aperture in a thin, planar frame by soldering leads at opposite ends of the plastic package to conductive pads on an upper surface of the frame adjacent the central aperture. Conductive traces and vias couple the conductive pads to other conductive pads on upper and lower surfaces of the frame adjacent outer edges thereof. The conductive pads adjacent the outer edges are soldered to the conductive pads of adjacent chip packages by dipping the edges of an assembled stack of the chip packages in solder. The chip stack thus formed is mounted on a substrate. Each chip package can be individually addressed by the substrate, such as to enable the chip therein, using a stair step arrangement of the conductive pads in which the pads on the opposite surfaces of each frame are coupled in offset fashion by vias extending through the frame.
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- 15 United States
- 10 France
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- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| OVID DATA CO LLC | 2711 CENTERVILLE RD SUITE 400 WILMINGTON DE 19808 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Eide, Floyd K | Huntington Beach, CA | 6 | 626 |
| Forthun, John A | Glendora, CA | 8 | 752 |
| Isaak, Harlan | Costa Mesa, CA | 2 | 198 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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