Importance

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Abstract

An integrated circuit device performing arithmetic operations on a plurality of digital inputs to produce an Effective Address and a Linear Address in parallel. The integrated circuit device comprises a first, second and third circuit. The first circuit includes a first adding circuit performs logical operations on the plurality of digital inputs (segment address, scaled index, displacement and segment base) to produce a first plurality of output signals for use in producing the Effective Address and another plurality of output signals to produce an uncorrected Linear Address. The uncorrected Linear Address, if accurate, should be equivalent to the arithmetic sum of the Effective Address and the segment base. Since the first circuit may produce an inaccurate uncorrected Linear Address as detected by a second circuit, the integrated circuit includes a third circuit, controlled by the second circuit, to subsequent modify the uncorrected Linear Address to obtain the Linear Address if the arithmetic sum of the Effective Address and the segment base is not equal to the uncorrected Linear Address.

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First Claim