Packet video signal inverse transport processor memory address circuitry
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United States of America Patent
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Mar 18, 1997
Issued Date -
N/A
app pub date -
Sep 13, 1995
filing date -
Apr 22, 1994
priority date (Note) -
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Abstract
In an inverse transport processor, program component packet payloads of respective program components are multiplexed to a memory data input port and directed to mutually exclusive areas of random access memory (RAM). The processor includes multiple direct memory access circuitry for writing the payloads of component data to the mutually exclusive blocks of the memory. Memory access for read and write functions are arbitrated so that no incoming program data can be lost, and all component processors are serviced.
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