Method of compressing data for use in performing VLSI mask layout verification
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United States of America Patent
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Mar 18, 1997
Issued Date -
N/A
app pub date -
Oct 19, 1995
filing date -
Nov 30, 1993
priority date (Note) -
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Abstract
A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.
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