Alignment accuracy check pattern
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United States of America Patent
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-
Mar 25, 1997
Issued Date -
N/A
app pub date -
May 16, 1996
filing date -
Dec 10, 1993
priority date (Note) -
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status (Latency Note)
Importance
Abstract
An alignment accuracy check pattern includes a contact hole formed in an insulating film on a major surface of a semiconductor substrate in a region different from an element region, and a photoresist for patterning which is formed in at least part of the contact hole. A wiring layer is formed under the insulating film, and another insulating film is formed under the wiring layer.
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