High speed programmable logic architecture
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United States of America Patent
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Mar 25, 1997
Issued Date -
N/A
app pub date -
Jun 5, 1995
filing date -
Jan 27, 1994
priority date (Note) -
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Abstract
Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.
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