Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 8, 1997
Grant Date -
N/A
app pub date -
Dec 23, 1994
filing date -
Dec 23, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully