Methods and apparatus for concurrent execution of serial computing instructions using combinatorial architecture for program partitioning
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 8, 1997
Grant Date -
N/A
app pub date -
Nov 25, 1994
filing date -
Nov 25, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computing system having a plurality of processing elements for concurrent execution of a serial program is able to run applications developed for single processors without change to source code or object code by allocating instructions to various processors depending upon the addresses contained within their operand(s). The memory space of the system is partitioned into individual memory blocks which are controlled by dedicated memory coordination units and plural memory coordination units are associated with each processor in a combinatorial connection arrangement. This allows instructions to execute on processors which inherently have all the information needed in their registers at the time of execution thus enhancing performance. The plurality of memory coordination units connected to a processing element are associated with FIFO queues which are utilized to ensure sequential consistency including the cases of indirect addressing and conditional jumps.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully