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Abstract

Method and apparatus for interconnecting integrated circuits (ICs) are described. The invented lattice preferably is formed in a plural-layer structure whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. Thousands of such horizontal layers are vertically stacked in the structure, each being shielded by voltage or ground planes and each being insulated by layers of insulative dielectric material. A regular array of vertical pillars is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The columns extend from the top of the substrate on which the ICs are mounted through to the bottom surface of the bottom layer. The pillars may be selectively disconnected from the layers by fusing techniques, or, alternatively, the pillars may be selectively connected to the layers by anti-fusing techniques. In one embodiment, the interconnection region between a pillar and a layer is switchably programmable to either interconnect or disconnect via a semiconductor switching device such as a transistor fabricated in the lattice interconnect structure, whereby each pillar's interface with each layer may be selectively and alterably defined as being conductive or insulative. Preferably, each column includes a bonding pad on the upper structure surface for surface mounting or wire bonding of selected I/O contacts of the ICs. Voltage and ground planes may be rendered in the same substrate by a technique involving the fusing or anti-fusing of selected vias so that they are electrically connected with a given plane representing a voltage or ground potential. Such also may be performed by forming vias and selectively plating them through, as by photolithographic techniques, to produce the desired connections.

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First Claim