Importance

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Abstract

A membrane probe (10) for simultaneously testing two or more columns or rows of integrated circuits (37) while still on the wafer (56) upon which they are manufactured includes a flexible visually clear and self planarizing membrane (18) having circuit traces (22). A substrate (12) on which the membrane (18) is mounted features parallel ports (14) corresponding to alternate columns or rows of circuit chips (37) on the wafer to be tested. Two such substrates (12,112) thus forming two alternately used probe test heads (10,110) are employed for testing each full wafer, one test head (10) containing ports (14) corresponding to one set of alternate wafer columns or rows, the other test head (110) containing ports (114) corresponding to the remaining interlaced wafer columns or rows. Probe contact pads (30) are electroplated on areas of the traces (22) so that the contact pads (30) are visually registrable through the substrate ports. The probe test heads (10,110) have a configuration, dimension and structure like that of the wafer (56) itself so that automated pick and place equipment employed for handling the wafers (56) may also be used to handle the probe test heads (10,110). A unique pair of test fixture inserts (34,134) is adapted to receive and detachably secure a selected probe test head (11,110) to the its corresponding test fixture insert.

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First Claim