Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier
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United States of America Patent
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Apr 22, 1997
Grant Date -
N/A
app pub date -
Jul 27, 1994
filing date -
Jul 27, 1994
priority date (Note) -
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Abstract
A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data value, and in response, creates a carry signal and a sum signal. The carry and sum signals are provided to input leads of the ALU. The ALU is used to add the carry and sum signals to create a third data value which is equal to the product of the first and second data values. In one embodiment, the input leads to the ALU are multiplexed. Thus, one input lead of the ALU receives either the carry signal or a signal from a first input node and the second input lead of the ALU receives either the sum signal or a signal from a second input node.
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