System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset

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United States of America Patent

PATENT NO 5623610
SERIAL NO

08332375

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhatt, Ajay V El Dorado Hills, CA 30 1444
Cadambi, Sudarshan B Portland, OR 7 778
Callahan, Shelagh Beaverton, OR 2 488
Knoll, Shaun Portland, OR 5 648
Morriss, Jeff C Boulder Creek, CA 17 645

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