US Patent No: 5,623,620
Number of patents in Portfolio can not be more than 2000
Special test modes for a page buffer shared resource in a memory device
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Apr 22, 1997
Issued date -
Jun 30, 1993
filing date -
08/085,542
serial no -
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Abstract
A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,053,990 Program/erase selection for flash memory | 245 | 1988 | |
| 5,065,364 Apparatus for providing block erasing in a flash EPROM | 163 | 1989 | |
| 5,159,672 Burst EPROM architecture | 14 | 1989 | |
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| 5,233,559 Row redundancy for flash memories | 51 | 1991 | |
| 5,249,158 Flash memory blocking architecture | 43 | 1991 | |
| 5,355,464 Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory | 74 | 1991 | |
| 5,265,059 Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory | 33 | 1991 | |
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| 5,377,199 Boundary test scheme for an intelligent device | 21 | 1993 | |
| 5,369,754 Block specific status information in a memory device | 75 | 1994 | |
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| 5,155,833 Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory | 33 | 1987 | |
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| 5,299,162 Nonvolatile semiconductor memory device and an optimizing programming method thereof | 115 | 1992 | |
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| 5,126,808 Flash EEPROM array with paged erase architecture | 190 | 1989 | |