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Abstract

A process for fabricating LDD-based MOS transistors. In the process, an active region is defined by forming a field oxide layer on a substrate. Next, a first gate oxide layer and a first polysilicon layer are formed on the substrate. A lithographic process is used to etch away part of the first gate oxide layer and the first polysilicon layer to expose areas where heavily doped source/drain regions are to be formed. A second polysilicon layer is formed and then ions are implanted to form heavily doped source/drain regions. The second polysilicon layer and the first polysilicon layer are then etched away to form a gate polysilicon layer and expose part of the gate oxide layer proximate to the heavily doped drain. One approach then involves depositing a second oxide layer and performing anisotropic etching on the second oxide layer to form first and second spacers on lateral sides of the gate, and finally implanting ions at slant angle with respect to the substrate into the heavily doped source and drain regions and area below portion of the oxide layer underlying the first spacer. Another approach involves implanting ions at normal angle with respect to the substrate into the heavily doped source/drain regions and area below the exposed portion of the gate oxide layer, thus forming the lightly doped drain.

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First Claim