Stabilizing the lock up of a bi-phase stable FPLL by augmenting a recovered DC pilot
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United States of America Patent
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May 6, 1997
Issued Date -
N/A
app pub date -
Dec 12, 1994
filing date -
Apr 4, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.
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