Importance

Loading Importance Indicators...

Abstract

Apparatus and method for hierarchical, centralized boundary-scan fault-testing of extended electronic circuits, including inter-board testing, within a unified, standard protocol. During this testing, each board is 'viewable' from the central test control in the same way that it is viewable when standing alone, before being incorporated into an extended system. The preferred embodiment of the invention is based on IEEE Std 1149.1, and is to be used with integrated circuits compliant with that standard. Because of this, the IEEE Std 1149.1 test elements--including but not limited to extensive micro-code--prepared for the testing of the board individually can be incorporated into the system-wide testing. The invention makes use of a 'parking' of integrated circuit test rings with any desired test vector in their boundary scan registers, so that they can subsequently be viewed from another board as part of inter-board fault testing. In its preferred embodiment the invention provides for the parallel coupling of all backplane slots to the standard test bus implicit in IEEE Std 1149.1. The coupling of test rings to the system test bus is through a SLOT Link apparatus that incorporates a Selection Controller (a three-state finite state machine in the preferred embodiment) for enabling one board to be selected for testing. an address facility ensuring that only one slot is selected at a time. Also included in the preferred embodiment test architecture on each board is a switching network and one or more Local Serial Port (LSP) Ring Controllers which, in the preferred embodiment, are four-state finite state machines. In this way a plurality of test rings on a single board can be flexibly configured for testing, so that a single test ring or several of the test rings in series are tested. These LSP Ring Controllers are also used to 'park' the Test Rings for subsequent inter-board testing.

Loading the Abstract Image...

First Claim