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Abstract

A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.

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