CMOS transistor network to gate level model extractor for simulation, verification and test generation
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United States of America Patent
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May 13, 1997
Issued Date -
N/A
app pub date -
Mar 17, 1995
filing date -
Oct 31, 1994
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Expired
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Abstract
A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.
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