Dynamic processor performance and power management in a computer system
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United States of America Patent
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May 13, 1997
Issued Date -
N/A
app pub date -
Feb 28, 1996
filing date -
Jun 17, 1994
priority date (Note) -
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Abstract
A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.
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