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Abstract

A method for forming a low voltage coefficient capacitor within an integrated circuit. Formed upon a semiconductor substrate is a first polysilicon layer. Formed directly upon the first polysilicon layer is an Inter Polysilicon Dielectric (IPD) layer. Formed directly upon the Inter Polysilicon Dielectric (IPD) layer is a second polysilicon layer. The first polysilicon layer and the second polysilicon layer each have a resistivity no greater than about 40 ohms per square. Formed directly upon the second polysilicon layer is an amorphous silicon layer. Formed directly upon the amorphous silicon layer is a metal layer which is capable of forming a metal silicide with the amorphous silicon layer. The thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer. Finally, the semiconductor substrate is annealed to form a metal silicide layer from the amorphous silicon layer and the metal layer.

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First Claim