Synchronous dual port RAM
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United States of America Patent
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May 20, 1997
Issued Date -
N/A
app pub date -
Jun 21, 1996
filing date -
Feb 10, 1995
priority date (Note) -
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Abstract
A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
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