Method and apparatus for testing redundant word and bit lines in a memory array
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United States of America Patent
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May 20, 1997
Grant Date -
N/A
app pub date -
Nov 28, 1995
filing date -
Nov 28, 1995
priority date (Note) -
Expired
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Abstract
A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.
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