Importance

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Abstract

A systolic array processor is provided which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD or the like. The processor is composed of a plurality of signal processors for performing signal processings for a plurality of signals including an analog signal or signals supplied as input signals thereto and determining analog outputs, a shift register array or shift register mesh consisting of a plurality of shift registers, and a timing controller for controlling signal processings, arithmetic additions, shift operations and sequences in time of control for shift directions, of the shift registers. The shift register array or mesh includes analog shift registers having functions of performing the addition of input signals, and the analog outputs are supplied to the analog shift registers as one input signals thereof, respectively.

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First Claim