Microprocessor with priority determination and priority based instruction selection
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United States of America Patent
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May 27, 1997
Grant Date -
N/A
app pub date -
Dec 13, 1991
filing date -
Dec 13, 1991
priority date (Note) -
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Abstract
A processor architecture comprises a priority processing unit (20), a priority memory (30), an instruction set memory (40), and an instruction execution unit (50). The priority processing unit (20) generates priority values and stores them in priority memory (30). Each priority value is associated with an instruction stored in instruction memory (40). Priority processing unit (20) causes the instruction associated with a particular priority value to be outputted to instruction execution unit (50).
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