Read and writable data bus particularly for programmable logic devices
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United States of America Patent
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Jun 3, 1997
Grant Date -
N/A
app pub date -
Feb 2, 1996
filing date -
Feb 2, 1996
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.
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