Importance

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Abstract

A programmable logic device (PLD) integrated circuit containing an array of fuse or anti-fuse links includes verification circuitry configured to classify link resistances after programing into three resistance zones, corresponding to a 'closed' state zone, an 'open' state zone and a 'forbidden' state zone intermediate the 'closed' and 'open' state zones. Two reference resistance values, namely a lower reference resistance value and the higher reference resistance value, divide the entire range of possible link resistance values into the aforementioned three resistance zones. Because the ratio between the higher reference resistance value and the lower reference resistance value is typically more than 50, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range. A measurement voltage produced in response to the link voltage is compared by a pair of differential comparators to respective lower and higher reference voltages, the lower reference voltage corresponding to the measurement voltage that would be produced by a higher link voltage that is the product of the higher reference resistance value and the lower current level, and the higher reference voltage corresponding to the measurement voltage that would be produced by a lower link voltage that is the product of the lower reference resistance value and the higher current level.

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First Claim