Importance

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Abstract

A synchronous dynamic random access memory (SDRAM) is responsive to command signals and includes a first bank memory array and a second bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an active command controlling an active operation on the first bank memory array and to initiate, in a second system clock cycle, a transfer read or write command controlling a read or write transfer operation for transferring data from or to the first bank memory array. The command controller responds to the active command to automatically initiate, in the second system clock cycle, a precharge command controlling a precharge operation on the second bank memory array.

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First Claim