Fast cycle time-low latency dynamic random access memories and systems and methods using the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 3, 1997
Grant Date -
N/A
app pub date -
Jan 11, 1996
filing date -
Jan 11, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Loading Importance Indicators... 
Abstract
A memory 200 comprising a plurality of rows and columns of memory cells, each column of cells associated with a conductive bitline 301. Memory 200 further includes precharge circuitry 204, 206 for precharging a selected one of the bitlines in response to a received control bit.
Loading the Abstract Image...
OK
First Claim
Family
Loading Family data...
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully