US Patent No: 5,638,334

Number of patents in Portfolio can not be more than 2000

Integrated circuit I/O using a high performance bus interface

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Abstract

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The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1317

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 63 4554
Horowitz, Mark Menlo Park, CA 89 4669

Cited Art Landscape

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS INCORPORATED (4)
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SAXPY COMPUTER, INC., A CA. CORP. (1)
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SPERRY RAND CORPORATION (1)
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TERADYNE, INC. (1)
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TEXTRON INC. (1)
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Tokyo Shibaura Denki Kabushiki Kaisha (1)
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TOPPAN PRINTING CO., LTD. (1)
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Other [Check patent profile for assignment information] (2)
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4,333,142 Self-configurable computer and memory system 55 1979

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (73)
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7,596,641 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2006
7,489,875 System and method for multiple bit optical data transmission in memory systems 1 2006
7,434,081 System and method for read synchronization of memory modules 2 2006
7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 10 2006
7,529,273 Method and system for synchronizing communications links in a hub-based memory system 5 2006
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7,411,807 System and method for optically interconnecting memory devices 3 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
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7,412,571 Memory arbitration system and method having an arbitration packet protocol 10 2007
7,823,024 Memory hub tester interface and method for use thereof 2 2007
7,774,559 Method and system for terminating write commands in a hub-based memory system 11 2007
8,082,404 Memory arbitration system and method having an arbitration packet protocol 2 2008
8,392,686 System and method for read synchronization of memory modules 1 2008
7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2009
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 2 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 2 2010
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8,438,329 System and method for optimizing interconnections of components in a multichip memory module 0 2011
8,712,249 Optical interconnect in high-speed memory systems 0 2011
8,346,998 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2011
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8,555,006 Memory arbitration system and method having an arbitration packet protocol 0 2011
8,694,735 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2012
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RAMBUS INC. (16)
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HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (2)
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INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
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Other [Check patent profile for assignment information] (1)
6,952,742 External storage device and method of accessing same 1 2004