Integrated circuit I/O using a high performance bus interface
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United States of America Patent
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Jun 10, 1997
Issued Date -
N/A
app pub date -
May 24, 1995
filing date -
Apr 18, 1990
priority date (Note) -
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Abstract
The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.
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