US Patent No: 5,638,334
Number of patents in Portfolio can not be more than 2000
Integrated circuit I/O using a high performance bus interface
Stats
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Jun 10, 1997
Issued date -
May 24, 1995
filing date -
08/448,657
serial no -
In Force
status
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Abstract
The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 4,306,298 Memory system for microprocessor with multiplexed address/data bus | 51 | 1979 | |
| 4,811,202 Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package | 93 | 1981 | |
| 4,443,864 Memory system for microprocessor with multiplexed address/data bus | 66 | 1981 | |
| 4,932,002 Bit line latch sense amp | 25 | 1988 | |
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| 4,595,923 Improved terminator for high speed data bus | 65 | 1984 | |
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| 4,286,321 Common bus communication system in which the width of the address field is greater than the number of lines on the bus | 75 | 1979 | |
| 4,649,516 Dynamic row buffer circuit for DRAM | 63 | 1984 | |
| 5,117,494 System for selectively detecting and bypassing inoperative module within a daisy chained processing system | 17 | 1987 | |
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| 4,488,218 Dynamic priority queue occupancy scheme for access to a demand-shared bus | 112 | 1982 | |
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| 4,775,931 Dynamically configured computing device | 72 | 1987 | |
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| 4,998,069 Loopback tester for testing field replaceable units | 19 | 1989 | |
| 5,012,408 Memory array addressing system for computer systems with multiple memory arrays | 82 | 1990 | |
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| 5,175,831 System register initialization technique employing a non-volatile/read only memory | 27 | 1989 | |
| 5,193,199 Device and method for programming critical hardware parameters | 26 | 1991 | |
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| 4,860,198 Microprocessor system | 142 | 1988 | |
| 5,410,512 Semiconductor memory device | 17 | 1993 | |
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| 4,249,247 Refresh system for dynamic RAM memory | 64 | 1979 | |
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| 4,635,192 Self configuring bus structure for computer network | 46 | 1983 | |
| 4,660,141 Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers | 120 | 1983 | |
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| 4,355,376 Apparatus and method for utilizing partially defective memory devices | 153 | 1980 | |
| 4,719,627 Memory system employing a low DC power gate array for error correction | 40 | 1986 | |
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| 4,421,996 Sense amplification scheme for random access memory | 28 | 1981 | |
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| 5,111,423 Programmable interface for computer system peripheral circuit card | 81 | 1988 | |
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| 4,706,166 High-density electronic modules--process and product | 240 | 1986 | |
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| 4,882,669 Multi computer fail safe control apparatus | 21 | 1987 | |
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| 5,040,153 Addressing multiple types of memory devices | 58 | 1990 | |
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| 4,785,394 Fair arbitration technique for a split transaction bus in a multiprocessor computer system | 175 | 1986 | |
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| 5,301,162 Semiconductor random access memory device having shared sense amplifiers serving as a cache memory | 46 | 1993 | |
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| 4,481,625 High speed data bus system | 170 | 1981 | |
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| 4,779,089 Bus arbitration controller | 102 | 1988 | |
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| 4,646,270 Video graphic dynamic RAM | 128 | 1983 | |
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| 4,758,993 Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays | 72 | 1985 | |
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| 4,649,511 Dynamic memory controller for single-chip microprocessor | 102 | 1983 | |
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| 4,571,672 Access control method for multiprocessor systems | 130 | 1983 | |
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| 4,933,835 Apparatus for maintaining consistency of a cache memory with a primary memory | 112 | 1989 | |
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| 5,038,320 Computer system with automatic initialization of pluggable option cards | 130 | 1989 | |
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| 4,468,738 Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors | 56 | 1983 | |
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| 4,263,650 Digital data processing system with interface adaptor having programmable, monitorable control register therein | 67 | 1979 | |
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| 4,818,985 Bus arbitration network capable of quickly carrying out arbitration among bus masters | 70 | 1987 | |
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| 5,038,317 Programmable controller module rack with a relative rack slot addressing mechanism | 41 | 1988 | |
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| 4,675,813 Program assignable I/O addresses for a computer | 28 | 1985 | |
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| 5,129,069 Method and apparatus for automatic memory configuration by a computer | 38 | 1989 | |
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| 4,837,682 Bus arbitration system and method | 98 | 1987 | |
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| 4,234,934 Apparatus for scaling memory addresses | 29 | 1978 | |
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| 4,247,817 Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver | 98 | 1978 | |
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| 4,630,193 Time multiplexed processor bus | 99 | 1982 | |
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| 4,354,258 Memory board automatically assigned its address range by its position | 22 | 1980 | |
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| 4,748,320 IC card | 143 | 1986 | |
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| 4,191,996 Self-configurable computer and memory system | 126 | 1977 | |
| 4,333,142 Self-configurable computer and memory system | 55 | 1979 | |