Integrated circuit I/O using a high performance bus interface

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5638334
SERIAL NO

08448657

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1476

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 59 4996
Horowitz, Mark Palo Alto, CA 78 5370

Cited Art Landscape

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Patent Citation Ranking

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