US Patent No: 5,638,334

Number of patents in Portfolio can not be more than 2000

Integrated circuit I/O using a high performance bus interface

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1353

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 59 4814
Horowitz, Mark Palo Alto, CA 77 5111

Cited Art Landscape

Patent Info (Count) # Cites Year
 
LORAL AEROSPACE CORPORATION (1)
* 4,468,738 Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors 57 1983
 
APROLASE DEVELOPMENT CO., LLC (1)
* 4,706,166 High-density electronic modules--process and product 282 1986
 
FREESCALE SEMICONDUCTOR, INC. (1)
* 4,646,270 Video graphic dynamic RAM 145 1983
 
ELPIDA MEMORY, INC. (1)
* 5,301,162 Semiconductor random access memory device having shared sense amplifiers serving as a cache memory 54 1993
 
Altera Corporation (1)
* 5,111,423 Programmable interface for computer system peripheral circuit card 97 1988
 
INTERGRAPH HARDWARE TECHNOLOGIES COMPANY (1)
* 4,933,835 Apparatus for maintaining consistency of a cache memory with a primary memory 112 1989
 
CHIPS AND TECHNOLOGIES, LLC (1)
* 5,040,153 Addressing multiple types of memory devices 60 1990
 
Datapoint Corporation (1)
* 4,785,394 Fair arbitration technique for a split transaction bus in a multiprocessor computer system 177 1986
 
TEXTRON INC. (1)
* 4,630,193 Time multiplexed processor bus 100 1982
 
NEC CORPORATION (1)
* 4,818,985 Bus arbitration network capable of quickly carrying out arbitration among bus masters 70 1987
 
TOPPAN PRINTING CO., LTD. (1)
* 4,748,320 IC card 152 1986
 
HITACHI MICROCOMPUTER ENGINEERING, LTD. (1)
* 4,571,672 Access control method for multiprocessor systems 145 1983
 
KABUSHIKI KAISHA TOSHIBA (2)
* 4,860,198 Microprocessor system 156 1988
* 5,410,512 Semiconductor memory device 17 1993
 
Bell Telephone Laboratories, Incorporated (2)
* 4,488,218 Dynamic priority queue occupancy scheme for access to a demand-shared bus 115 1982
* 4,745,548 Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters 56 1987
 
Canon Kabushiki Kaisha (1)
* 4,882,669 Multi computer fail safe control apparatus 21 1987
 
GENERAL ELECTRIC COMPANY (1)
* 4,649,511 Dynamic memory controller for single-chip microprocessor 102 1983
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 4,649,516 Dynamic row buffer circuit for DRAM 64 1984
* 5,117,494 System for selectively detecting and bypassing inoperative module within a daisy chained processing system 17 1987
 
F. & S. CORPORATION OF COLUMBUS, (1)
* 4,779,089 Bus arbitration controller 103 1988
 
ADVANCED MICRO DEVICES, INC. (1)
* 4,421,996 Sense amplification scheme for random access memory 29 1981
 
HEWLETT-PACKARD COMPANY (2)
* 4,775,931 Dynamically configured computing device 80 1987
* 5,371,892 Method for configuring a computer bus adapter circuit board without the use of jumpers or switches 36 1992
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (2)
* 4,998,069 Loopback tester for testing field replaceable units 20 1989
* 5,012,408 Memory array addressing system for computer systems with multiple memory arrays 94 1990
 
IXYS INTL LIMITED (2)
* 5,175,831 System register initialization technique employing a non-volatile/read only memory 28 1989
* 5,193,199 Device and method for programming critical hardware parameters 28 1991
 
Tri Sigma Corporation (2)
* 4,635,192 Self configuring bus structure for computer network 46 1983
* 4,660,141 Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers 124 1983
 
Tokyo Shibaura Denki Kabushiki Kaisha (1)
* 4,354,258 Memory board automatically assigned its address range by its position 22 1980
 
Nippondenso Co., Ltd. (1)
* 5,038,317 Programmable controller module rack with a relative rack slot addressing mechanism 41 1988
 
LENOVO (SINGAPORE) PTE LTD. (1)
* 5,038,320 Computer system with automatic initialization of pluggable option cards 135 1989
 
FUJITSU LIMITED (1)
* 4,758,993 Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays 81 1985
 
SAXPY COMPUTER, INC., A CA. CORP. (1)
* 4,837,682 Bus arbitration system and method 100 1987
 
INTEL CORPORATION (2)
* 4,449,207 Byte-wide dynamic RAM with multiplexed internal buses 63 1982
* 4,595,923 Improved terminator for high speed data bus 65 1984
 
RPX CORPORATION (1)
* 5,129,069 Method and apparatus for automatic memory configuration by a computer 38 1989
 
Texas Instruments Incorporated (3)
* 4,811,202 Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package 93 1981
* 4,443,864 Memory system for microprocessor with multiplexed address/data bus 66 1981
* 4,932,002 Bit line latch sense amp 25 1988
 
ELXSI CORPORATION, A DE CORP. (1)
* 4,481,625 High speed data bus system 179 1981
 
UNISYS CORPORATION (2)
* 4,355,376 Apparatus and method for utilizing partially defective memory devices 160 1980
* 4,719,627 Memory system employing a low DC power gate array for error correction 40 1986
 
NORTEL NETWORKS LIMITED (1)
* 4,675,813 Program assignable I/O addresses for a computer 28 1985
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
* 5,870,616 System and method for reducing power consumption in an electronic circuit 35 1996
 
Other [Check patent profile for assignment information] (9)
6,952,742 External storage device and method of accessing same 1 2004
* 2004/0167,994 External storage device and method of accessing same 0 2004
* 2005/0060,487 Memory device having a power down exit register 11 2004
* 2005/0120,161 Methods of operation of a memory device and system 2 2004
* 2005/0154,817 Method of operation and controlling a memory device 1 2005
* 2005/0146,944 Memory module and method having on-board data search capabilities and processor-based system using such memory modules 9 2005
* 2005/0146,943 Memory module and method having on-board data search capabilities and processor-based system using such memory modules 12 2005
* 2005/0193,183 Method and apparatus for initializing dynamic random access memory (DRAM) devices 58 2005
* 2005/0235,130 System for a memory device having a power down mode and method 1 2005
 
YAMAHA CORPORATION (1)
* 5,857,083 Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus 39 1996
 
OPTi Inc. (1)
7,523,245 Compact ISA-bus interface 2 2006
 
ROUND ROCK RESEARCH, LLC (105)
7,133,972 Memory hub with internal cache and/or memory access prediction 105 2002
* 2003/0229,770 Memory hub with internal cache and/or memory access prediction 22 2002
7,149,874 Memory hub bypass circuit and method 15 2002
* 2004/0034,753 Memory hub bypass circuit and method 16 2002
7,245,145 Memory module and method having improved signal routing topology 14 2003
* 2004/0251,929 MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY 8 2003
7,120,727 Reconfigurable memory module and method 160 2003
7,428,644 System and method for selective memory module power management 81 2003
7,260,685 Memory hub and access method having internal prefetch buffers 37 2003
7,107,415 Posted write buffers and methods of posting write requests in memory modules 29 2003
* 2004/0260,909 Memory hub and access method having internal prefetch buffers 8 2003
* 2004/0260,891 Posted write buffers and methods of posting write requests in memory modules 1 2003
7,389,364 Apparatus and method for direct memory access in a hub-based memory system 2 2003
* 2005/0021,884 Apparatus and method for direct memory access in a hub-based memory system 9 2003
7,210,059 System and method for on-board diagnostics of memory modules 100 2003
7,133,991 Method and system for capturing and bypassing memory transactions in a hub-based memory system 18 2003
* 2005/0044,304 Method and system for capturing and bypassing memory transactions in a hub-based memory system 5 2003
7,136,958 Multiple processor system and method including multiple memory hub modules 43 2003
* 2005/0050,255 Multiple processor system and method including multiple memory hub modules 7 2003
7,310,752 System and method for on-board timing margin testing of memory modules 7 2003
* 2005/0060,600 System and method for on-board timing margin testing of memory modules 1 2003
7,194,593 Memory hub with integrated non-volatile memory 38 2003
7,120,743 Arbitration system and method for memory responses in a hub-based memory system 61 2003
* 2005/0086,441 Arbitration system and method for memory responses in a hub-based memory system 10 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 17 2003
7,181,584 Dynamic command and/or address mirroring system and method for memory modules 47 2004
* 2005/0177,690 Dynamic command and/or address mirroring system and method for memory modules 7 2004
7,120,723 System and method for memory hub-based expansion bus 26 2004
* 2005/0216,648 System and method for memory hub-based expansion bus 11 2004
7,213,082 Memory hub and method for providing memory sequencing hints 26 2004
6,980,042 Delay line synchronizer apparatus and method 60 2004
* 2005/0218,956 DELAY LINE SYNCHRONIZER APPARATUS AND METHOD 3 2004
7,162,567 Memory hub and method for memory sequencing 40 2004
7,180,522 Apparatus and method for distributed memory control in a graphics processing system 16 2004
* 2005/0030,313 Apparatus and method for distributed memory control in a graphics processing system 6 2004
7,242,213 Memory module and method having improved signal routing topology 12 2004
7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture 7 2004
* 2005/0066,137 Method and system for controlling memory accesses to memory modules having a memory hub architecture 9 2004
7,047,351 Memory hub bypass circuit and method 50 2005
7,222,197 Apparatus and method for direct memory access in a hub-based memory system 4 2005
* 2005/0160,201 Apparatus and method for direct memory access in a hub-based memory system 2 2005
7,282,947 Memory module and method having improved signal routing topology 11 2005
7,605,631 Delay line synchronizer apparatus and method 5 2005
* 2006/0066,375 Delay line synchronizer apparatus and method 18 2005
8,589,643 Arbitration system and method for memory responses in a hub-based memory system 3 2005
7,415,567 Memory hub bypass circuit and method 7 2006
7,222,210 System and method for memory hub-based expansion bus 10 2006
7,206,887 System and method for memory hub-based expansion bus 44 2006
7,174,409 System and method for memory hub-based expansion bus 10 2006
* 2006/0195,647 System and method for memory hub-based expansion bus 4 2006
* 2006/0179,203 System and method for memory hub-based expansion bus 2 2006
7,418,526 Memory hub and method for providing memory sequencing hints 27 2006
7,490,211 Memory hub with integrated non-volatile memory 4 2006
* 2006/0200,620 Memory hub with integrated non-volatile memory 6 2006
7,251,714 Method and system for capturing and bypassing memory transactions in a hub-based memory system 10 2006
7,689,879 System and method for on-board timing margin testing of memory modules 6 2006
7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules 3 2006
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 7 2006
7,437,579 System and method for selective memory module power management 70 2006
7,278,060 System and method for on-board diagnostics of memory modules 4 2006
* 2006/0206,766 System and method for on-board diagnostics of memory modules 1 2006
7,412,566 Memory hub and access method having internal prefetch buffers 16 2006
* 2007/0011,392 Reconfigurable memory module and method 4 2006
7,386,649 Multiple processor system and method including multiple memory hub modules 22 2006
7,353,320 Memory hub and method for memory sequencing 8 2006
* 2007/0033,353 Memory hub and method for memory sequencing 7 2006
7,644,253 Memory hub with internal cache and/or memory access prediction 1 2006
7,546,435 Dynamic command and/or address mirroring system and method for memory modules 3 2007
7,370,134 System and method for memory hub-based expansion bus 26 2007
7,716,444 Method and system for controlling memory accesses to memory modules having a memory hub architecture 4 2007
7,516,363 System and method for on-board diagnostics of memory modules 4 2007
* 2008/0016,401 System and method for on-board diagnostics of memory modules 5 2007
7,557,601 Memory module and method having improved signal routing topology 3 2007
7,581,055 Multiple processor system and method including multiple memory hub modules 6 2007
7,818,712 Reconfigurable memory module and method 0 2008
7,562,178 Memory hub and method for memory sequencing 3 2008
7,610,430 System and method for memory hub-based expansion bus 9 2008
7,966,430 Apparatus and method for direct memory access in a hub-based memory system 0 2008
* 2009/0327,532 APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM 1 2008
8,127,081 Memory hub and access method having internal prefetch buffers 0 2008
7,913,122 System and method for on-board diagnostics of memory modules 0 2008
7,945,737 Memory hub with internal cache and/or memory access prediction 0 2009
7,975,122 Memory hub with integrated non-volatile memory 0 2009
* 2009/0132,781 MEMORY HUB WITH INTEGRATED NON-VOLATILE MEMORY 0 2009
7,746,095 Memory module and method having improved signal routing topology 4 2009
7,873,775 Multiple processor system and method including multiple memory hub modules 1 2009
8,164,375 Delay line synchronizer apparatus and method 1 2009
7,899,969 System and method for memory hub-based expansion bus 0 2009
7,958,412 System and method for on-board timing margin testing of memory modules 3 2010
* 2010/0153,794 SYSTEM AND METHOD FOR ON-BOARD TIMING MARGIN TESTING OF MEMORY MODULES 2 2010
7,908,452 Method and system for controlling memory accesses to memory modules having a memory hub architecture 0 2010
7,966,444 Reconfigurable memory module and method 2 2010
* 2011/0029,746 RECONFIGURABLE MEMORY MODULE AND METHOD 1 2010
8,244,952 Multiple processor system and method including multiple memory hub modules 0 2011
* 2011/0113,189 MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES 0 2011
8,086,815 System for controlling memory accesses to memory modules having a memory hub architecture 2 2011
8,195,918 Memory hub with internal cache and/or memory access prediction 0 2011
8,209,445 Apparatus and method for direct memory access in a hub-based memory system 0 2011
8,200,884 Reconfigurable memory module and method 4 2011
8,832,404 Memory hub with integrated non-volatile memory 0 2011
8,117,371 System and method for memory hub-based expansion bus 0 2011
8,234,479 System for controlling memory accesses to memory modules having a memory hub architecture 1 2011
8,499,127 Memory hub with internal cache and/or memory access prediction 0 2012
8,732,383 Reconfigurable memory module and method 2 2012
9,082,461 Multiple processor system and method including multiple memory hub modules 0 2012
 
U.S. BANK NATIONAL ASSOCIATION (6)
* 2004/0257,890 Wavelength division multiplexed memory module, memory system and method 3 2004
* 2005/0223,161 Memory hub and access method having internal row caching 43 2005
* 2006/0218,331 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 4 2006
* 2006/0204,247 System and method for multiple bit optical data transmission in memory systems 23 2006
* 2006/0218,318 Method and system for synchronizing communications links in a hub-based memory system 17 2006
* 2011/0231,618 OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS 1 2011
 
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (2)
6,728,860 Address mapping in solid state storage device 3 2001
6,931,509 Address mapping in solid state storage device 11 2003
 
TANISYS TECHNOLOGY, INC. (2)
* 6,285,962 Method and system for testing rambus memory modules 26 1999
6,480,799 Method and system for testing RAMBUS memory modules 3 2001
 
Micron Technology, Inc. (79)
* 5,734,661 Method and apparatus for providing external access to internal integrated circuit test circuits 24 1996
7,941,056 Optical interconnect in high-speed memory systems 4 2001
* 2003/0101,312 Machine state storage apparatus and method 7 2001
7,200,024 System and method for optically interconnecting memory devices 26 2002
* 2004/0024,959 System and method for optically interconnecting memory devices 10 2002
7,117,316 Memory hub and access method having internal row caching 24 2002
* 2004/0024,978 Memory hub and access method having internal row caching 6 2002
7,254,331 System and method for multiple bit optical data transmission in memory systems 14 2002
* 2004/0028,412 System and method for multiple bit optical data transmission in memory systems 7 2002
6,944,743 Memory hub bypass circuit and method 0 2002
7,836,252 System and method for optimizing interconnections of memory devices in a multichip module 1 2002
* 2004/0044,833 System and method for optimizing interconnections of memory devices in a multichip module 119 2002
* 2004/0047,169 Wavelength division multiplexed memory module, memory system and method 13 2002
6,937,057 Memory module and method having improved signal routing topology 0 2003
7,366,920 System and method for selective memory module power management 0 2003
* 2005/0050,237 Memory module and method having on-board data search capabilities and processor-based system using such memory modules 63 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,330,992 System and method for read synchronization of memory modules 9 2003
* 2005/0149,774 System and method for read synchronization of memory modules 10 2003
7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers 43 2004
* 2005/0172,084 Buffer control system and method for a memory system having memory request buffers 9 2004
7,788,451 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 16 2004
7,412,574 System and method for arbitration of memory responses in a hub-based memory system 23 2004
* 2005/0177,695 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 24 2004
7,257,683 Memory arbitration system and method having an arbitration packet protocol 14 2004
* 2005/0216,677 Memory arbitration system and method having an arbitration packet protocol 5 2004
7,447,240 Method and system for synchronizing communications links in a hub-based memory system 7 2004
* 2005/0213,611 Method and system for synchronizing communications links in a hub-based memory system 7 2004
7,590,797 System and method for optimizing interconnections of components in a multichip memory module 1 2004
7,222,213 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 38 2004
* 2005/0257,021 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 5 2004
7,363,419 Method and system for terminating write commands in a hub-based memory system 37 2004
* 2005/0268,060 Method and system for terminating write commands in a hub-based memory system 10 2004
7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers 7 2004
7,310,748 Memory hub tester interface and method for use thereof 12 2004
* 2005/0286,506 System and method for an asynchronous data buffer having buffer write and read pointers 33 2004
* 2005/0283,681 Memory hub tester interface and method for use thereof 4 2004
7,106,611 Wavelength division multiplexed memory module, memory system and method 25 2004
7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture 12 2004
* 2006/0047,891 System and method for transmitting data packets in a computer system having a memory hub architecture 4 2004
* 2006/0168,407 Memory hub system and method having large virtual page size 66 2005
7,289,347 System and method for optically interconnecting memory devices 10 2005
8,954,687 Memory hub and access method having a sequencer and internal row caching 0 2005
7,272,682 Memory hub bypass circuit and method 0 2006
7,870,329 System and method for optimizing interconnections of components in a multichip memory module 4 2006
7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers 2 2006
7,805,586 System and method for optimizing interconnections of memory devices in a multichip module 4 2006
7,596,641 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2006
7,489,875 System and method for multiple bit optical data transmission in memory systems 1 2006
7,434,081 System and method for read synchronization of memory modules 4 2006
7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 11 2006
7,529,273 Method and system for synchronizing communications links in a hub-based memory system 7 2006
7,411,807 System and method for optically interconnecting memory devices 4 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
8,504,782 Buffer control system and method for a memory system having outstanding read and write request buffers 2 2007
7,412,571 Memory arbitration system and method having an arbitration packet protocol 13 2007
* 2007/0180,171 Memory arbitration system and method having an arbitration packet protocol 5 2007
7,823,024 Memory hub tester interface and method for use thereof 3 2007
7,774,559 Method and system for terminating write commands in a hub-based memory system 12 2007
8,082,404 Memory arbitration system and method having an arbitration packet protocol 4 2008
* 2008/0294,856 MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL 2 2008
* 2008/0294,862 ARBITRATION SYSTEM HAVING A PACKET MEMORY AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM 6 2008
8,392,686 System and method for read synchronization of memory modules 3 2008
7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2009
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 3 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 4 2010
8,190,819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
8,438,329 System and method for optimizing interconnections of components in a multichip memory module 0 2011
8,712,249 Optical interconnect in high-speed memory systems 1 2011
8,346,998 System and method for transmitting data packets in a computer system having a memory hub architecture 2 2011
8,775,764 Memory hub architecture having programmable lane widths 0 2011
8,555,006 Memory arbitration system and method having an arbitration packet protocol 0 2011
8,694,735 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2012
8,880,833 System and method for read synchronization of memory modules 0 2013
8,788,765 Buffer control system and method for a memory system having outstanding read and write request buffers 0 2013
9,032,166 Memory arbitration system and method having an arbitration packet protocol 0 2013
9,164,937 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2014
9,299,423 Optical interconnect in high-speed memory systems 1 2014
9,274,991 Memory hub architecture having programmable lane widths 0 2014
 
GLOBALFOUNDRIES INC. (1)
* 5,896,404 Programmable burst length DRAM 65 1997
 
RAMBUS INC. (23)
* 6,085,284 Method of operating a memory device having a variable data output length and an identification register 26 1999
* 6,842,864 Method and apparatus for configuring access times of memory devices 43 2000
* 6,546,446 Synchronous memory device having automatic precharge 62 2001
7,574,616 Memory device having a power down exit register 2 2004
8,127,152 Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode 2 2004
7,571,330 System and module including a memory device having a power down mode 2 2005
7,581,121 System for a memory device having a power down mode and method 60 2005
7,464,225 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 86 2005
7,729,151 System including a buffered memory module 9 2006
* 2007/0088,995 SYSTEM INCLUDING A BUFFERED MEMORY MODULE 94 2006
7,562,271 Memory system topologies including a buffer device and an integrated circuit memory device 15 2007
* 2008/0080,261 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 22 2007
7,526,597 Buffered memory having a control bus and dedicated data lines 14 2007
* 2008/0034,130 Buffered Memory Having A Control Bus And Dedicated Data Lines 29 2007
7,523,248 System having a controller device, a buffer device and a plurality of memory devices 4 2008
* 2008/0144,411 Memory Module Including A Plurality Of Integrated Circuit Memory Devices And A Plurality Of Buffer Devices In A Matrix Topology 21 2008
* 2009/0319,719 System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices 3 2009
7,685,364 Memory system topologies including a buffer device and an integrated circuit memory device 4 2009
8,108,607 Memory system topologies including a buffer device and an integrated circuit memory device 2 2010
8,539,152 Memory system topologies including a buffer device and an integrated circuit memory device 0 2011
* 2011/0228,614 Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device 2 2011
8,756,395 Controlling DRAM at time DRAM ready to receive command when exiting power down 0 2012
9,117,035 Memory system topologies including a buffer device and an integrated circuit memory device 0 2013
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (1)
6,182,254 Rambus ASIC having high speed testing function and testing method thereof 9 1998
* Cited By Examiner