Importance

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Abstract

Method and apparatus for distributing bus loading in a data processing system (11, 13, 15). In one embodiment, the present invention uses a bus loading control register bit field (90) to determine how address and data will be transferred over busses (60, 62) in order to allow more equal distribution of loads on the busses (60, 62). There is no fixed address bus or data bus. Instead, on a per cycle basis, each generic bus (60, 62) can be individually programmed to transfer address only, data only, both address and data, or neither address nor data. In one embodiment, there is a programmable address range (150-153) which corresponds to each bus loading bit field (90-93). For a bus access to a particular address range, the corresponding bus loading bit field (e.g. 90) is used to determine how address and data are transferred across the busses (60, 62).

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First Claim