Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing synchronization
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United States of America Patent
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Jun 10, 1997
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jun 7, 1995
priority date (Note) -
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Abstract
A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Any graphics subsystem must be able to support a variety of video formats, causing video refresh logic to become complicated. Such potential complications are avoided by the provision of a simple, general purpose hardware refresh system based on the direct color graphics frame buffer, with the broader range of services being provided by emulation using one of the processors included in the device.
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