US Patent No: 5,638,534

Number of patents in Portfolio can not be more than 2000

Memory controller which executes read and write commands out of order

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ATTORNEY / AGENT: (SPONSORED)
 

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Abstract

A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ACCENTUS PLCDIDCOT OXFORDSHIRE OX11 0QJ65
SAMSUNG ELECTRONICS CO., LTD.SUWON-SI GYEONGGI-DO45244

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mote, Jr L Randall Laguna Hills, CA 14 516

Cited Art

Patent Info (Count) # Cites Year
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (4)
5,193,167 Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system 93 1990
5,263,144 Method and apparatus for sharing data between processors in a computer system 20 1990
5,289,584 Memory system with FIFO data input 62 1991
5,388,247 History buffer control to reduce unnecessary allocations in a memory stream buffer 36 1994
 
MITSUBISHI DENKI KABUSHIKI KAISHA (3)
4,926,385 Semiconductor memory device with cache memory addressable by block within each column 76 1988
5,226,139 Semiconductor memory device with a built-in cache memory and operating method thereof 41 1991
5,206,834 Semiconductor memory device performing last in-first out operation and the method for controlling the same 11 1992
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,023,776 Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage 152 1988
5,278,967 System for providing gapless data transfer from page-mode dynamic random access memories 35 1990
 
SAMSUNG ELECTRONICS CO., LTD. (2)
5,247,643 Memory control circuit for optimizing copy back/line fill operation in a copy back cache system 37 1991
5,487,049 Page-in, burst-out FIFO 49 1994
 
CVSI, INC. (1)
4,959,771 Write buffer for a digital processing system 28 1989
 
DELL USA, L.P. (1)
5,485,589 Predictive addressing architecture 34 1994
 
HEWLETT-PACKARD COMPANY (1)
5,022,004 Method and apparatus for DRAM memory performance enhancement 29 1988
 
HITACHI, LTD. (1)
5,479,635 Memory device including DRAMs for high-speed accessing 30 1994
 
HONEYWELL INFORMATION SYSTEMS INC. (1)
4,181,974 System providing multiple outstanding information requests 32 1978
 
LENOVO (SINGAPORE) PTE LTD. (1)
5,034,917 Computer system including a page mode memory with decreased access time and method of operation thereof 90 1988
 
LG ELECTRONICS INC. (1)
5,379,379 Memory control unit with selective execution of queued read and write requests 62 1990
 
LIYUE CAPITAL, LLC (1)
5,524,220 Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems 38 1994
 
NEC CORPORATION (1)
4,538,226 Buffer control system 22 1984
 
NIPPON ELECTRIC CO., LTD. (1)
4,429,375 Consecutive addressing of a semiconductor memory 30 1981
 
SKYPIX JOINT VENTURE, L.P. (1)
5,247,355 Gridlocked method and system for video motion compensation 30 1992
 
SUN MICROSYSTEMS, INC. (1)
5,265,236 Method and apparatus for increasing the speed of memory access in a virtual memory system having fast page mode 33 1993
 
TANDON CORPORATION (1)
5,325,499 Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory 73 1990
 
WESTERN DIGITAL TECHNOLOGIES, INC. (1)
5,072,420 FIFO control architecture and method for buffer memory access arbitration 95 1989

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (52)
6,286,062 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus 2 1997
7,035,962 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus 2 1999
6,963,949 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus 1 1999
6,418,495 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus 2 1999
6,292,877 Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus 56 1999
6,247,070 Pipelined packet-oriented memory system having a undirectional command and address bus and a bidirectional data bus 2 1999
7,133,972 Memory hub with internal cache and/or memory access prediction 86 2002
7,245,145 Memory module and method having improved signal routing topology 10 2003
7,120,727 Reconfigurable memory module and method 112 2003
7,428,644 System and method for selective memory module power management 42 2003
7,260,685 Memory hub and access method having internal prefetch buffers 31 2003
7,107,415 Posted write buffers and methods of posting write requests in memory modules 21 2003
7,389,364 Apparatus and method for direct memory access in a hub-based memory system 2 2003
7,136,958 Multiple processor system and method including multiple memory hub modules 31 2003
7,120,743 Arbitration system and method for memory responses in a hub-based memory system 47 2003
7,213,082 Memory hub and method for providing memory sequencing hints 17 2004
6,980,042 Delay line synchronizer apparatus and method 45 2004
7,162,567 Memory hub and method for memory sequencing 33 2004
7,180,522 Apparatus and method for distributed memory control in a graphics processing system 5 2004
7,242,213 Memory module and method having improved signal routing topology 9 2004
7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2004
7,047,351 Memory hub bypass circuit and method 42 2005
7,222,197 Apparatus and method for direct memory access in a hub-based memory system 3 2005
7,282,947 Memory module and method having improved signal routing topology 8 2005
7,605,631 Delay line synchronizer apparatus and method 4 2005
7,415,567 Memory hub bypass circuit and method 2 2006
7,418,526 Memory hub and method for providing memory sequencing hints 25 2006
7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules 1 2006
7,437,579 System and method for selective memory module power management 36 2006
7,412,566 Memory hub and access method having internal prefetch buffers 14 2006
7,386,649 Multiple processor system and method including multiple memory hub modules 15 2006
7,353,320 Memory hub and method for memory sequencing 2 2006
7,644,253 Memory hub with internal cache and/or memory access prediction 1 2006
7,716,444 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2007
7,557,601 Memory module and method having improved signal routing topology 2 2007
7,581,055 Multiple processor system and method including multiple memory hub modules 3 2007
7,818,712 Reconfigurable memory module and method 0 2008
7,562,178 Memory hub and method for memory sequencing 1 2008
7,966,430 Apparatus and method for direct memory access in a hub-based memory system 0 2008
8,127,081 Memory hub and access method having internal prefetch buffers 0 2008
7,945,737 Memory hub with internal cache and/or memory access prediction 0 2009
7,746,095 Memory module and method having improved signal routing topology 2 2009
7,873,775 Multiple processor system and method including multiple memory hub modules 0 2009
8,164,375 Delay line synchronizer apparatus and method 0 2009
7,908,452 Method and system for controlling memory accesses to memory modules having a memory hub architecture 0 2010
7,966,444 Reconfigurable memory module and method 0 2010
8,244,952 Multiple processor system and method including multiple memory hub modules 0 2011
8,086,815 System for controlling memory accesses to memory modules having a memory hub architecture 1 2011
8,195,918 Memory hub with internal cache and/or memory access prediction 0 2011
8,209,445 Apparatus and method for direct memory access in a hub-based memory system 0 2011
8,200,884 Reconfigurable memory module and method 2 2011
8,234,479 System for controlling memory accesses to memory modules having a memory hub architecture 0 2011
 
MICRON TECHNOLOGY, INC. (25)
6,378,047 System and method for invalidating set-associative cache memory with simultaneous set validity determination 16 1997
6,460,114 Storing a flushed cache line in a memory buffer of a controller 74 1999
7,200,024 System and method for optically interconnecting memory devices 22 2002
7,117,316 Memory hub and access method having internal row caching 14 2002
7,836,252 System and method for optimizing interconnections of memory devices in a multichip module 1 2002
7,366,920 System and method for selective memory module power management 0 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,330,992 System and method for read synchronization of memory modules 4 2003
7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers 34 2004
7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers 4 2004
7,106,611 Wavelength division multiplexed memory module, memory system and method 20 2004
7,289,347 System and method for optically interconnecting memory devices 7 2005
7,272,682 Memory hub bypass circuit and method 0 2006
7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers 1 2006
7,805,586 System and method for optimizing interconnections of memory devices in a multichip module 2 2006
7,434,081 System and method for read synchronization of memory modules 1 2006
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
7,411,807 System and method for optically interconnecting memory devices 2 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
8,082,404 Memory arbitration system and method having an arbitration packet protocol 0 2008
8,392,686 System and method for read synchronization of memory modules 0 2008
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 0 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2010
8,190,819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
 
INTEL CORPORATION (9)
5,996,042 Scalable, high bandwidth multicard memory system utilizing a single memory controller 8 1996
6,092,158 Method and apparatus for arbitrating between command streams 182 1997
6,088,772 Method and apparatus for improving system performance when reordering commands 31 1997
6,243,781 Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe 20 1998
6,782,457 Prioritized bus request scheduling mechanism for processing devices 12 2003
7,133,981 Prioritized bus request scheduling mechanism for processing devices 4 2004
7,970,989 Write ordering on disk cached platforms 1 2006
7,836,380 Destination indication to aid in posted write buffer loading 1 2006
7,487,305 Prioritized bus request scheduling mechanism for processing devices 4 2006
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (4)
5,784,582 Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline 67 1996
6,269,433 Memory controller using queue look-ahead to reduce memory latency 23 1998
6,279,065 Computer system with improved memory access 14 1998
6,385,676 Coherent ordering queue for computer system 7 1999
 
ARM LIMITED (3)
6,490,655 Data processing apparatus and method for cache line replacement responsive to the operational state of memory 33 1999
7,020,751 Write back cache memory control within data processing system 4 2002
6,684,302 Bus arbitration circuit responsive to latency of access requests and the state of the memory circuit 13 2002
 
CYPRESS SEMICONDUCTOR CORPORATION (3)
6,292,403 Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method 12 2000
6,445,645 Random access memory having independent read port and write port and process for writing to and reading from the same 2 2001
6,385,128 Random access memory having a read/write address bus and process for writing to and reading from the same 12 2001
 
APPLE INC. (2)
7,996,599 Command resequencing in memory operations 0 2007
8,166,236 Merging command signals for memory cells 0 2011
 
A-DATA TECHNOLOGY CO., LTD. (1)
8,375,159 Electronic storage device and control method thereof 0 2009
 
ADVANCED MICRO DEVICES, INC. (1)
7,127,573 Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions 4 2000
 
HITACHI, LTD. (1)
5,809,539 Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs 14 1996
 
INFINEON TECHNOLOGIES AG (1)
6,510,474 Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests 18 1999
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
8,082,396 Selecting a command to send to memory 0 2005
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
6,145,065 Memory access buffer and reordering apparatus using priorities 89 1998
 
NEC CORPORATION (1)
8,225,064 Storage region allocation system, storage region allocation method, and control apparatus 0 2006
 
NETLIST, INC. (1)
8,417,870 System and method of increasing addressable memory space on a memory board 0 2009
 
NXP B.V. (1)
6,008,823 Method and apparatus for enhancing access to a shared memory 11 1995
 
SAMSUNG ELECTRONICS CO., LTD. (1)
7,133,231 Method and apparatus for recording data on hard disk drive, and storage medium therefor 1 2005
 
SUN MICROSYSTEMS, INC. (1)
6,601,151 Apparatus and method for handling memory access requests in a data processing system 25 1999
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
6,272,600 Memory request reordering in a data processing system 30 1997