US Patent No: 5,639,697

Number of patents in Portfolio can not be more than 2000

Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

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Abstract

A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NXP B.V.EINDHOVEN3593

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bothra, Subhas Fremont, CA 96 1408
Gabriel, Calvin T Cupertino, CA 68 1014
Weling, Milind G San Jose, CA 17 258

Cited Art

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,476,817 Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers 74 1994
 
UNISYS CORPORATION (1)
4,916,514 Integrated circuit employing dummy conductors for planarity 70 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (12)
5,981,384 Method of intermetal dielectric planarization by metal features layout modification 36 1995
6,331,488 Planarization process for semiconductor substrates 111 1997
5,965,940 Intermetal dielectric planarization by metal features layout modification 17 1997
6,218,316 Planarization of non-planar surfaces in device fabrication 146 1998
6,448,591 Metallization line layout 90 1999
6,518,172 Method for applying uniform pressurized film across wafer 8 2000
6,403,499 Planarization of non-planar surfaces in device fabrication 9 2001
6,743,724 Planarization process for semiconductor substrates 4 2001
6,653,722 Method for applying uniform pressurized film across wafer 14 2002
6,743,644 Method of making a metallization line layout 2 2002
6,677,252 Methods for planarization of non-planar surfaces in device fabrication 56 2002
6,828,227 Method for applying uniform pressurized film across wafer 2 2002
 
ROUND ROCK RESEARCH, LLC (9)
6,036,586 Apparatus and method for reducing removal forces for CMP pads 69 1998
6,062,133 Global planarization method and apparatus 36 1999
6,398,905 Apparatus and method for reducing removal forces for CMP pads 9 2000
6,237,483 Global planarization method and apparatus 87 2000
6,683,003 Global planarization method and apparatus 1 2001
6,814,834 Apparatus and method for reducing removal forces for CMP pads 3 2002
6,991,740 Method for reducing removal forces for CMP pads 2 2004
7,585,425 Apparatus and method for reducing removal forces for CMP pads 1 2006
8,308,528 Apparatus and method for reducing removal forces for CMP pads 0 2009
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (4)
5,747,382 Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching 19 1996
6,239,023 Method to reduce the damages of copper lines 0 1999
6,413,863 Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process 8 2000
6,500,753 Method to reduce the damages of copper lines 2 2001
 
INFINEON TECHNOLOGIES AG (3)
7,071,074 Structure and method for placement, sizing and shaping of dummy structures 7 2003
7,494,930 Structure and method for placement, sizing and shaping of dummy structures 0 2006
7,868,427 Structure and method for placement, sizing and shaping of dummy structures 0 2009
 
MOSAID TECHNOLOGIES INCORPORATED (3)
6,316,363 Deadhesion method and mechanism for wafer processing 15 1999
6,506,679 Deadhesion method and mechanism for wafer processing 9 2001
6,693,034 Deadhesion method and mechanism for wafer processing 1 2002
 
AGERE SYSTEMS INC. (2)
6,436,807 Method for making an interconnect layer and a semiconductor device including the same 7 2000
6,683,382 Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills 6 2002
 
INTEL CORPORATION (2)
6,025,254 Low resistance gate electrode layer and method of making same 8 1997
6,365,521 Passivation for tight metal geometry 2 1997
 
LSI LOGIC CORPORATION (2)
6,867,127 Diamond metal-filled patterns achieving low parasitic coupling capacitance 6 2002
6,998,716 Diamond metal-filled patterns achieving low parasitic coupling capacitance 3 2004
 
MITSUBISHI DENKI KABUSHIKI KAISHA (2)
6,303,944 Method of manufacturing a semiconductor device having a monitor pattern, and a semiconductor device manufactured thereby 2 1998
6,602,725 Method of manufacturing a semiconductor device having a monitor pattern, and a semiconductor device manufactured thereby 4 2001
 
NEOPHOTONICS CORPORATION (2)
6,690,025 Devices for etch loading planar lightwave circuits 3 2001
7,182,878 Methods for etch loading planar lightwave circuits 0 2004
 
NXP B.V. (2)
5,861,342 Optimized structures for dummy fill mask design 44 1995
6,319,796 Manufacture of an integrated circuit isolation structure 12 1999
 
YAMAHA CORPORATION (2)
6,080,652 Method of fabricating a semiconductor device having a multi-layered wiring 5 1998
5,998,814 Semiconductor device and fabrication method thereof 6 1998
 
ADVANCED MICRO DEVICES, INC. (1)
5,840,623 Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP 2 1995
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (1)
6,380,087 CMP process utilizing dummy plugs in damascene process 43 2000
 
FELLOWS RESEARCH B.V., LLC (1)
5,976,928 Chemical mechanical polishing of FeRAM capacitors 107 1997
 
NIJMEGEN, UNVERSITY MEDICAL CENTER, UNIVERSITY OF, THE (1)
6,633,084 Semiconductor wafer for improved chemical-mechanical polishing over large area features 19 1999
 
PHILIPS ELECTRONICS NORTH AMERICA CORPORATION (1)
6,323,113 Intelligent gate-level fill methods for reducing global pattern density effects 50 1999
 
QIMONDA AG (1)
5,972,787 CMP process using indicator areas to determine endpoint 7 1998
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,518,157 Methods of planarizing insulating layers on regions having different etching rates 1 2001
 
SANDISK 3D LLC (1)
7,291,562 Method to form topography in a deposited layer above a substrate 0 2005
 
SEIKO EPSON CORPORATION (1)
7,679,109 Semiconductor device, layout design method thereof, and layout design device using the same 0 2007
 
UNITED MICROELECTRONICS CORP. (1)
6,303,484 Method of manufacturing dummy pattern 2 2000