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Abstract

A bus with selective burst ordering enables the implementation of computer systems that incorporate bus masters (e.g., processors, DMA controllers, LAN controllers, etc.) with dissimilar burst orders. The same bus supports devices which require or prefer differing burst orders for high bandwidth data transfers. Selective burst order is enabled through the use of a bus line which may be asserted by the current bus master. By asserting the corresponding signal, a current bus master indicates that sequential (rather than non-sequential) burst order will be used for data transfer. Specialized burst address generation logic enables a bus slave to generate, in the selected burst order, the low order bits of memory addresses for the data words implicitly addressed during a burst transfer.

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First Claim