The present invention relates to a variable-length code decoding circuit for decoding an input variable-length code string and a variable-length code decoding system using the same. A typical variable-length code decoding circuit of the present invention includes a CAM cell 10 for storing a variable-length code bit and a RAM cell 20 which is paired with the CAM cell 10 for storing a mask bit so as to perform a masking operation. The variable-length code decoding circuit further includes an NMOS transistor 30 which is coupled between the CAM cell 10 and a match line ML for selectively disconnecting the CAM cell 10 from the match line ML in response to an output of the RAM cell 20. The CAM cell 10 collates a bit of the input variables-length code string with the stored code bit. When the input bit matches the stored code bit, the CAM cell 10 outputs an H level matching to the match line ML and otherwise it outputs an L level unmatching to the match line ML. If the CAM cell 10 does not relate to the collating operation that is, if it does not matter whether there is a match, the RAM cell 20 corresponding to the CAM cell 10 outputs an L level signal to turn off the NMOS transistor 30. When the NMOS 30 is turned off, the output of the CAM cell 10 is not transmitted to the match line ML.
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