System for network transmission using a communication co-processor comprising a microprocessor to implement protocol layer and a microprocessor to manage DMA
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United States of America Patent
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Jun 24, 1997
Grant Date -
N/A
app pub date -
Aug 22, 1994
filing date -
Dec 22, 1992
priority date (Note) -
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Abstract
A system for transmitting data (NCC) between a computer bus (PSB) and a network (RE), including (1) a general purpose unit (GPU) connected to the bus and to a network-connected adapter, and including a first microprocessor and a unit for transferring frames between the bus and the adapter, and vice versa, comprising a dual port memory connected therebetween; and (2) a communication coprocessor (PPA) connected to the general purpose unit (GPU). Said coprocessor (PPA) includes a second microprocessor (CPU.sub.3) implementing, for each communication layer (C.sub.2 -C.sub.4), the corresponding protocol by providing each frame with control data adapted to said protocol, said second microprocessor being connected to the first microprocessor and the memory; and a third microprocessor (CPU.sub.4) providing direct memory access management of data transfer between the second microprocessor (CPU.sub.3) and the memory (VRAM).
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