
US Patent No: 5,644,515
Number of patents in Portfolio can not be more than 2000
Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation
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Jul 1, 1997
Issued date -
Jun 7, 1995
filing date -
08/483,337
serial no -
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Abstract
A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 4,306,286 Logic simulation machine | 172 | 1979 | |
| 4,357,678 Programmable sequential logic array mechanism | 35 | 1979 | |
| 4,386,403 System and method for LSI circuit analysis | 47 | 1979 | |
| 4,404,635 Programmable integrated circuit and method of testing the circuit before it is programmed | 29 | 1981 | |
| 4,503,386 Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | 63 | 1982 | |
| 4,656,580 Logic simulation machine | 111 | 1982 | |
| 4,593,363 Simultaneous placement and wiring for VLSI chips | 152 | 1983 | |
| 4,862,347 System for simulating memory arrays in a logic simulation machine | 101 | 1986 | |
| 4,695,999 Cross-point switch of multiple autonomous planes | 64 | 1986 | |
| 4,849,904 Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices | 53 | 1987 | |
| 5,003,487 Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis | 91 | 1988 | |
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| 4,541,071 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates | 41 | 1983 | |
| 4,782,440 Logic simulator using small capacity memories for storing logic states, connection patterns, and logic functions | 45 | 1985 | |
| 4,752,887 Routing method for use in wiring design | 71 | 1986 | |
| 4,747,102 Method of controlling a logical simulation at a high speed | 32 | 1986 | |
| 4,945,503 Hardware simulator capable of reducing an amount of information | 42 | 1987 | |
| 4,924,429 Hardware logic simulator | 50 | 1988 | |
| 5,041,986 Logic synthesis system comprising a memory for a reduced number of translation rules | 32 | 1989 | |
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| 4,642,487 Special interconnect for configurable logic array | 396 | 1984 | |
| 4,695,740 Bidirectional buffer amplifier | 51 | 1984 | |
| 4,706,216 Configurable logic element | 471 | 1985 | |
| 4,758,985 Microprocessor oriented configurable logic element | 251 | 1986 | |
| 4,713,557 Bidirectional buffer amplifier | 101 | 1987 | |
| 4,855,669 System for scan testing of logic circuit networks | 84 | 1987 | |
| 4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects | 678 | 1988 | |
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| 4,525,789 Programmable network tester with data formatter | 29 | 1982 | |
| 4,578,761 Separating an equivalent circuit into components to detect terminating networks | 30 | 1983 | |
| 4,577,276 Placement of components on circuit substrates | 118 | 1983 | |
| 4,908,772 Integrated circuits with component placement by rectilinear partitioning | 135 | 1987 | |
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| 4,697,241 Hardware logic simulator | 105 | 1985 | |
| 4,914,612 Massively distributed simulation engine | 78 | 1988 | |
| 5,109,353 Apparatus for emulation of electronic hardware system | 177 | 1988 | |
| 5,036,473 Method of using electronically reconfigurable logic circuits | 243 | 1989 | |
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| 4,758,745 User programmable integrated circuit interconnect architecture and test method | 440 | 1986 | |
| 4,873,459 Programmable interconnect architecture | 343 | 1988 | |
| 5,083,083 Testability architecture and techniques for programmable interconnect architecture | 107 | 1989 | |
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| 4,700,187 Programmable, asynchronous logic cell and array | 138 | 1985 | |
| 4,918,440 Programmable logic cell and array | 151 | 1986 | |
| 4,845,633 System for programming graphically a programmable, asynchronous logic cell and array | 70 | 1987 | |
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| 4,942,536 Method of automatic circuit translation | 56 | 1986 | |
| 4,803,636 Circuit translator | 54 | 1986 | |
| 5,046,017 Wiring design for semiconductor integrated circuit | 58 | 1988 | |
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| 4,761,768 Programmable logic device | 185 | 1985 | |
| 4,766,569 Programmable logic array | 121 | 1986 | |
| 4,864,165 ECL programmable logic array with direct testing means for verification of programmed state | 49 | 1988 | |
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| 4,942,615 Gate processor arrangement for simulation processor system | 38 | 1988 | |
| 4,972,372 Programmable device and method of testing programmable device | 60 | 1988 | |
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| 4,674,089 In-circuit emulator | 177 | 1985 | |
| 5,023,775 Software programmable logic array utilizing "and" and "or" gates | 103 | 1990 | |
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| 4,787,061 Dual delay mode pipelined logic simulator | 55 | 1986 | |
| 4,744,084 Hardware modeling system and method for simulating portions of electrical circuits | 129 | 1987 | |
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| 4,835,705 Interconnection area decision processor | 53 | 1987 | |
| 4,876,466 Programmable logic array having a changeable logic structure | 107 | 1988 | |
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| 5,093,920 Programmable processing elements interconnected by a communication network including field operation unit for performing field operations | 46 | 1989 | |
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| 4,949,275 Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same | 52 | 1985 | |
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| 4,931,946 Programmable tiles | 50 | 1988 | |
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| 4,725,835 Time multiplexed bus matrix switching system | 88 | 1985 | |
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| 4,621,339 SIMD machine using cube connected cycles network architecture for vector processing | 157 | 1983 | |
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| 4,510,602 Programmable logic apparatus for entering, processing and transmitting data | 20 | 1982 | |
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| 4,935,734 Semi-conductor integrated circuits/systems | 145 | 1986 | |
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| 2002/0186,837 Multiple prime number generation using a parallel prime number search algorithm | 2001 | ||
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| 4,882,690 Incremental logic synthesis method | 81 | 1986 | |
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| 4,918,594 Method and system for logical simulation of information processing system including logic circuit model and logic function model | 53 | 1987 | |
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| 4,613,940 Method and structure for use in designing and building electronic systems in integrated circuits | 75 | 1982 | |
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| 4,722,084 Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits | 61 | 1985 | |
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| 4,823,276 Computer-aided automatic wiring method for semiconductor integrated circuit device | 48 | 1987 | |
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| 4,600,846 Universal logic circuit modules | 37 | 1983 | |
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| 4,901,259 Asic emulator | 82 | 1988 | |
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| 4,791,602 Soft programmable logic array | 60 | 1986 | |
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| 4,527,115 Configurable logic gate array | 33 | 1982 | |
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| 4,901,260 Bounded lag distributed discrete event simulation method and apparatus | 65 | 1987 | |
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| 4,365,294 Modular terminal system using a common bus | 69 | 1980 | |
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| 4,777,606 Method for deriving an interconnection route between elements in an interconnection medium | 141 | 1986 | |
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| 4,811,214 Multinode reconfigurable pipeline computer | 209 | 1986 | |
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| 4,768,196 Programmable logic array | 54 | 1986 | |
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| 4,612,618 Hierarchical, computerized design of integrated circuits | 106 | 1983 | |
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| 4,815,003 Structured design method for high density standard cell and macrocell layout of VLSI chips | 142 | 1987 | |
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| 4,922,432 Knowledge based method and apparatus for designing integrated circuits using functional specifications | 169 | 1988 | |
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| 4,488,354 Method for simulating and testing an integrated circuit chip | 61 | 1981 | |
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| 4,958,324 Method for the testing of electrically programmable memory cells, and corresponding integrated circuit | 33 | 1988 | |
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| 4,459,694 Field programmable device with circuitry for detecting poor insulation between adjacent word lines | 21 | 1981 | |
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| 4,951,220 Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems | 37 | 1988 | |
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| 4,740,919 Electrically programmable logic array | 35 | 1986 | |
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| 4,656,592 Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit | 101 | 1984 | |
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| 4,675,832 Visual display logic simulation system | 75 | 1984 | |
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| 4,965,739 Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected | 75 | 1989 | |
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| 5,253,363 Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array | 29 | 1990 | |
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| 4,786,904 Electronically programmable gate array having programmable interconnect lines | 166 | 1986 | |
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| 4,539,564 Electronically controlled interconnection system | 28 | 1982 | |
| 4,682,440 Animal trap | 28 | 1986 | |
| 4,849,928 Logic array programmer | 41 | 1987 | |
| 4,827,427 Instantaneous incremental compiler for producing logic circuit designs | 101 | 1987 | |
| 5,051,938 Simulation of selected logic circuit designs | 118 | 1989 | |