Flash memory system, and methods of constructing and utilizing same
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United States of America Patent
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Jul 1, 1997
Issued Date -
N/A
app pub date -
Apr 26, 1995
filing date -
Nov 2, 1992
priority date (Note) -
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Abstract
An N-channel SNOS or SONOS type memory array (100) has programmable states with a negative, depletion mode threshold lower in magnitude than the supply voltage V.sub.CC when erased and a positive threshold when programmed. During reading, the supply voltage V.sub.CC is applied to the drain (16), while a positive voltage V.sub.R less than V.sub.CC -V.sub.ds,sat is applied to the source (14), where V.sub.ds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have V.sub.R applied to the gate (12), while inhibited devices have ground or the substrate potential V.sub.SS applied to the gate (12).
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