Processor structure and method for a time-out checkpoint

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United States of America Patent

PATENT NO 5644742
SERIAL NO

08473223

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Abstract

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Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, end such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITED1-1 KAMIKODANAKA 4-CHOME NAKAHARA- KU KAWASAKI-SHI KANAGAWA 211-8588 211-8588

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Patkar, Niteen A Sunnyvale, CA 11 547
Shebanow, Michael C Plano, TX 48 1512
Shen, Gene W Mountain View, CA 21 874
Szeto, John Oakland, CA 10 384

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