Integrated circuit data processor with selectable routing of data accesses
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United States of America Patent
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Jul 1, 1997
Grant Date -
N/A
app pub date -
Apr 7, 1995
filing date -
Apr 7, 1995
priority date (Note) -
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Abstract
An integrated circuit data processor (30) includes a central processing; unit (31) with separate internal instruction (32) and load/store (33) buses. The data processor (30) includes a nonvolatile memory (34) connected to the instruction bus (32). In a first mode of operation, a system integration unit (36) allows cross-bus accesses from the load/store bus (33) to the nonvolatile memory (34) on the instruction bus (32). These cross-bus accesses allow the central processing unit (31) to access system parameters from the same nonvolatile memory (34) which stores the program. In a second mode of operation, a control bit in the system integration unit (36) routes accesses from the load/store bus (33) to the nonvolatile memory (34) off-chip. The central processing unit (31) continues to access instructions from the nonvolatile memory (34) in the second mode. In this way, system parameters normally stored in the nonvolatile memory (34) may be accurately calibrated.
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