Mixed mode output buffer circuit for CMOSIC
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United States of America Patent
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Jul 8, 1997
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N/A
app pub date -
Jun 13, 1996
filing date -
Aug 7, 1995
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Abstract
This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.
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