CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors
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United States of America Patent
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Jul 8, 1997
Grant Date -
N/A
app pub date -
Mar 26, 1996
filing date -
Mar 26, 1996
priority date (Note) -
Expired
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Abstract
An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.
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