Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
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United States of America Patent
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Jul 8, 1997
Grant Date -
N/A
app pub date -
Oct 18, 1995
filing date -
Oct 25, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associated with the respective semiconductor memory modules, and a timing varying unit for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.
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